The present invention relates to a phase locked loop (hereinafter, referred to as xe2x80x9cPLLxe2x80x9d) using a variable frequency oscillator, particularly to a variable frequency oscillator preferably applied to a semiconductor integrated circuit device operated at low power supply voltage.
A large-scaled semiconductor integrated circuit device (hereinafter, referred to as xe2x80x9cLSIxe2x80x9d) integrated with a microprocessor has been developed intensively and large scale formation, high speed formation and low power consumption have been achieved and are being improved. A microprocessor is an operation device for executing operations as instructed by a program or the like and is operated in synchronism with clocks. A frequency synthesizer using a PLL is well known as a circuit for generating clocks (refer to, for example, D. Mijuskovic et al. xe2x80x9cCell Based Fully Integrated CMOS Frequency Synthesizerxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. SC-29 (issued in March, 1994), p.271-p.279). FIG. 11 shows a constitution of a frequency synthesizer generally used in LSI.
In FIG. 11, a feedback loop is formed by a phase detector 1, a loop filter 3 and a current controlled oscillator 7. The current controlled oscillator 7 (hereinafter, abbreviated as xe2x80x9cICOxe2x80x9d) outputs a clock signal fvco in synchronism with a reference signal fr from outside. ICO 7 is a variable frequency oscillator for changing an oscillation frequency in accordance with an input current. Further, a divider 9 is a divider for generating the reference signal for dividing an input signal fi at a low frequency inputted from a quartz oscillator or the like from the outside. A divider 8 is a divider for feedback inserted into the feedback loop and by pertinently setting respective numbers of divisions of both, the clock signal fvco at a predetermined frequency can be provided. Further, a comparison signal fp to the phase detector 1 is outputted from the divider 8.
In this case, the basic function of the constitution shown by FIG. 11 resides in PLL for forming a signal the phase of which is synchronized with that of the input signal by the feedback loop. Installation of the dividers 8 and 9 is arbitrary and PLL functions particularly as a frequency synthesizer by installing these. Further, PLL constitutes a clock generating circuit when an output signal is a clock signal.
When such a frequency synthesizer is formed by LSI, there is adopted a constitution in consideration of special properties of a semiconductor integrated circuit. That is, in a semiconductor integrated circuit, there is a case in which although a capacitor is easy to provide, a resistor is difficult to form and formation of inductance is very difficult. Hence, the loop filter 3 is formed by a capacitor, charge and discharge of a current to and from the capacitor is carried out by a charge pump 2 and the loop filter 3 is bypassed by installing an auxiliary charge pump (hereinafter, abbreviated as xe2x80x9cACPxe2x80x9d) 5. ACP 5 executes an operation equivalent to that of a resistor and forms a zero point in a transfer function of the feedback loop. By providing the zero point, the feedback loop is stabilized.
The phase detector 1 detects a phase difference between the reference signal fr and the output signal fp of the divider 8 and outputs UP signal (a control signal for increasing a frequency) and DN signal (a signal decreasing a frequency) for controlling ICO 7. Further, at the same time, ICO 7 outputs UPB signal and DNB signal which respectively constitute inverted signals of UP signal and DN signal. The UP signal and DN signal are pulse width modulation signals in correspondence with the phase difference between the reference signal fr and the comparison signal fp.
Further, when ICO 7 is constituted of a semiconductor integrated circuit, there is a tendency in which improvement of linearity of a relationship between an oscillation frequency and a current is more facilitated than that of a relationship between an oscillation frequency and a voltage and accordingly, ICO 7 is adopted more preferably than a voltage controlled oscillator (VCO) and a voltage-to-current converter (hereinafter, abbreviated as xe2x80x9cVICxe2x80x9d) 4 converts a voltage across terminals of a capacitor of the loop filter 3 into a current. Further, ACP 5 is constituted to output a current and accordingly, the output currents from the VIC 4 and ACP 5 are added at an adder 6 for forming the above-described bypass.
Next, an explanation will be given of principal circuits of such PLL. FIG. 12 shows constitutions of the charge pump 2 and the loop filter 3. The charge pump 2 is constituted of switches 12 and 13 comprising 2 sets of transistors and current sources 10 and 11 and inputs UP signal and DNB signal from the phase detector 1. In this case, UP signal and DN signal are effective when they are 0. Further, the loop filter 3 is connected to an output of the charge pump 2 and is constituted of a capacitor Cp.
The charge pump 2 charges and discharges electric charge in correspondence with inputted UP signal and inputted DNB signal from electric charge stored in the capacitor Cp of the loop filter 3. In this case, amounts of electric charge which are charged and discharged become values derived from current values Iup and Idn of the current sources 10 and 11 constituting the charge pump 2 multiplied by a difference between a pulse width of UP signal and a pulse width of DNB signal.
FIG. 13 shows an example of VIC 4 for converting a voltage across terminals of a capacitor into a current (refer to, for example, Ilya Novof xe2x80x9cFully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and xc2x150 ps Jitterxe2x80x9d, IEEE ISSCC ""95 Digest Technical Papers (issued in February, 1995) p.112-p.113).
Such VIC is provided with a circuit constitution in which 3 stages or more of transistors each operating in a saturation region are cascaded and 3 V or more of power supply voltage is needed.
Successively, owing to special properties of a semiconductor integrated circuit mentioned above and a request for high speed operation, ICO 7 is normally constituted of a ring oscillator which plural delay cells of a current control type having gain are cascaded and the output of the final stage delay cell is fed back to the input of the first delay cell (refer to, for example, B. Razavi xe2x80x9cDesign of Monolithic Phase-Locked Loops and Clock Recovery Circuitsxe2x80x9d, p.1-p.39, issued by IEEE Press, 1996).
FIG. 14 shows an example of a delay cell. Transistors M21 and M22 for inputting differential signals Vin signal polarities of which are inverted each other and outputting divided signals Vout constitute a differential amplifier and transistors M23 and M24 constitute load resistances of these. Transistors M25 and M26 connected to respective output terminals of the differential amplifier constitute a positive feedback circuit and negative resistance formed by the positive feedback cancels the above-described load resistances. Thereby, the load resistances are increased apparently. Further, each of the transistors M25 and M26 is an amplifier having a gate electrode as an input terminal and a drain electrode as an output terminal and the positive feedback circuit is constituted of connecting the input and output terminals to intersect with each other.
Transistors M27 and M28 for inputting a frequency control signal Vcont respectively change a common source current of the transistors M23 and M24 and a common source current of the transistors M25 and M26 and change the apparent load resistances mentioned above. Although not illustrated, the output terminal of the amplifier is provided with parasitic capacitance and a time constant is formed by the parasitic capacitance and the apparent load resistance, and the time constant is changed by changing the apparent load resistance. That is, a delay amount of the delay cell is changed by current to thereby change the oscillation frequency of ICO 7 which is a ring oscillator in which the plural delay cells are cascaded and the output of the final stage delay cell is fed back to the input of the first stage delay cell.
According to the delay cell of FIG. 14, power supply voltage is restrained low by constructing a constitution in which the transistors M27 and M28 are not cascaded to the transistors M21 and M22. However, the transistors of the amplifier and the current source are used in the saturation region, the output terminal of the amplifier is connected to an input terminal of an amplifier of a delay cell at a post stage and the like, accordingly, the power source voltage needs to be about 3 times as much as gate-to-source voltage of the transistor, specifically 2.5 V at minimum.
According to LSI integrated with a microprocessor, dimensions of a semiconductor element become very small in accordance with large scale formation and accordingly, transistor breakdown voltage is lowered and low voltage formation of power supply has been progressed. The voltage which used to be 5 V has become 3 V and recently, there is a trend of lowering the voltage to about 1 V. Further, low voltage formation of power supply directly contributes to a reduction in power consumption of LSI. Further, other than large scale formation of LSI, in accordance with enlargement of application, there has been an increase in the operational speed and enlargement of a frequency variable range.
According to the conventional respective circuits mentioned above, an object of the power source voltage is around 3 V and when the power source voltage is lowered to about 1 V, the following problem is posed.
According to ICO 7, the gain of the delay cell is reduced by lowering the operational current of the transistor and the gain of the delay cell at a vicinity of oscillation frequency may become lower than 1. In this case, the variable range of the frequency is narrowed and depending on cases, the oscillation may be stopped. As a countermeasure, although a method of increasing a cascade stage number of delay cells is conceivable, the upper limit of the oscillation frequency is lowered, power consumption is increased and accordingly, the method cannot be regarded as an appropriate improvement.
According to VIC 4, a transistor which has been operated in the saturation region shifts to a resistor region (non-saturation region) and in the procedure, the voltage-to-current conversion having excellent linearity cannot be executed.
Next, with regard to the variable range of the oscillation frequency, according to the circuit constitution bypassed by ACP 5 shown by FIG. 11, there is a problem stated below where widening of the variable range is difficult.
When UP signal or DN signal is generated, the current is instantaneously added and accordingly, the oscillation frequency is brought into a state in which it jumps to change for a short period of time. In this case, when a normal frequency is designated by notation of and its period is designated by notation T and an instantaneous amount of frequency change and an instantaneous amount of period change are respectively designated by notations xcex94f and xcex94T, the following equation (1) is established.
xcex94T/T≈f/ofxe2x80x83xe2x80x83(1)
Accordingly, when UP signal and DN signal are added or subtracted relatedly as they are as in the case of using conventional ACP 5, xcex94f stays constant and accordingly, an error xcex94T/T of period is increased as of becomes lower. That is, jitter (fluctuation over time) is increased. There is an allowable limit in the magnitude of jitter and therefore, fo cannot be lowered to a certain degree or less and the variable range of the oscillation frequency is narrowed.
It is an object of the invention to resolve the above-described problems of the conventional technologies and to provide a novel variable frequency oscillator capable of oscillating at a high frequency as well as PLL and a clock synchronizer using thereof and having a wide oscillation frequency range.
The most significant feature of the present invention resides in that a variable frequency oscillator adopts delay cells each constituted such that a complementary amplifier having an input terminal by connecting together gate electrodes of a pMOS (Metal Oxide Semiconductor) and an nMOS transistor and an output terminal by connecting together drain electrodes thereof is adopted as an amplifier element, a differential amplifier and a positive feedback circuit connected with input and output terminals intersected with each other are constituted of using the complementary amplifiers, the positive feedback circuit is connected between the output terminals of the differential amplifier and a controlling MOS transistor for controlling source currents of the complementary amplifiers and the complimentary amplifiers are connected in series between a power supply terminal and a ground terminal.
According to the constitution of the delay cells, source electrodes of the pMOS transistors of the complementary amplifiers used in the differential amplifier and the positive feedback circuit are connected together, further, source electrodes of the nMOS transistors are connected together. Further, a frequency control signal is supplied to a gate electrode of the controlling MOS transistor and a drain current of the controlling MOS transistor constitutes a control current for controlling source currents of the complementary amplifiers.
The complementary amplifier can be used as an inverter in which when one transistor is brought into an ON state (resistor region), other transistor is brought into an OFF state. According to the present invention, by using the complementary amplifier as such an inverter, the differential amplifier constitutes a differential circuit of the inverters states of which are inverted from each other and the positive feedback circuit constitutes a latch circuit. Accordingly, voltage for operating the differential amplifier and the positive feedback circuit can be made voltage for bringing one transistor into an ON state, that is, substantially threshold voltage of the transistor (application of voltage is not necessary to a transistor in an OFF state). Specifically, the voltage is about 0.7 V.
In the meantime, although it is necessary to maintain the saturation region in the controlling MOS transistor for controlling the source currents of the complementary amplifiers, the drain-to-source voltage therefor becomes about 0.3 V. Accordingly, the delay cell according to the present invention becomes operable by power source voltage of 1 V produced by adding 0.3 V to the above-described threshold voltage 0.7 V.
Next, the positive feedback circuit detects a very small voltage difference outputted from the differential amplifier and accelerates the output terminal to change in a direction from power source potential to ground potential or a direction reverse thereto and accordingly, the delay cell can not only be provided with high gain apparently but also can execute high speed operation. Further, a number of stages of cascading the delay cells can be reduced.
In this way, according to the variable frequency oscillator constituted of using the delay cells of the present invention, lowering of gain is not caused under low power supply voltage and the oscillator oscillates stably.
Other feature of the present invention resides in that a circuit comprising a first MOS transistor the gate electrode of which is biased to voltage higher than that of the drain voltage and a second MOS transistor in which an output voltage of a loop filter is inputted to the gate electrode, an output current is outputted from the drain electrode and the source electrode is connected to the drain electrode of the first MOS transistor, constitutes a voltage-to-current converting unit of a voltage-to-current converter. The above-described bias can be realized by, for example, connecting the gate electrode to power supply.
The transistor biased as mentioned above operates in the resistor region and conducts a behavior substantially the same as that of a resistor at low voltage of power supply voltage of about 1 V. By constituting a source resistor by such a resistor, according to the second MOS transistor, linear voltage-to-current conversion can be carried out under low power supply voltage. Thereby, a converted current having a wide linear range is obtained and a wide operational range of PLL is ensured in accordance therewith.
Still other feature of the present invention resides in that an auxiliary charge pump is constituted of a first current source and a second current source, a first differential circuit for inputting UP signal and UPB signal and switching a current of the first current source, a second differential circuit for inputting DN signal and DNB signal and switching a current of the second current source and a current mirror circuit for copying a current outputted from the second differential circuit when DN signal is effective, and a terminal constituted of connecting a terminal to which the second differential circuit outputs the current when UP signal is effective and a terminal to which the current mirror circuit outputs the copied current constitutes an output terminal of the auxiliary charge pump and further preferably, the currents of the first current source and the second current source are changed in proportion to an output signal of the loop filter.
By setting such a proportional relationship, according to PLL having the proposed auxiliary charge pump, xcex94f of the above-described Equation (1) becomes proportional to fo and the period error xcex94T/T becomes constant regardless of the frequency. Therefore, even when the oscillation frequency is reduced, jitter is not increased and PLL can obtain a wide oscillation frequency range.
These and other objects and many of the attendant advantages of the invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings.